 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET TDA8020HL Dual smart card interface Product specification Supersedes data of 2001 May 29 File under Integrated Circuits, IC02 2001 Aug 15 Philips Semiconductors Product specification Dual smart card interface FEATURES * Two independent 6 contacts smart card interfaces * Supply voltage to the cards; VCC = 5 or 3 V 5%; ICC up to 65 mA * Integrated DC/DC converter (doubler, tripler or follower) for allowing power supply from 2.5 to 6.5 V * Independant supply voltage for interface signals (from 1.5 to 6.5 V) * Control and status via the I2C-bus * Four possible devices in parallel due to two I2C-bus address pins * Electrical specifications according to ISO 7816 or EMV norms * Automatic activation and deactivation sequences by means of integrated sequencers * Automatic clock count and reset toggling during warm or cold reset * Interrupt request output to the controller * 6 kV ESD protection on cards contacts * Automatic emergency deactivation in the event of supply drop-out, overload, overheating or card take-off * Current limitation on pins CLK, RST, I/O and VCC * Integrated voltage supervisor for power-on reset and drop-out detection * Power-down mode with several wake-up events. ORDERING INFORMATION TYPE NUMBER TDA8020HL PACKAGE NAME LQFP32 DESCRIPTION APPLICATIONS * Set top boxes * Banking terminals * Internet terminals. GENERAL DESCRIPTION TDA8020HL The TDA8020HL is a one-chip dual smart card interface. Controlled by the I2C-bus, it guarantees conformity to ISO 7816 or EMV norms with very few external components. VERSION SOT358-1 plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm 2001 Aug 15 2 Philips Semiconductors Product specification Dual smart card interface QUICK REFERENCE DATA SYMBOL VDD VDDI IDD PARAMETER supply voltage on pins VDD and VDDA supply voltage for interface signals supply current (IDD and IDDA) VDD = 3.3 V; inactive mode VDD = 3.3 V; Power-down mode; 2 cards activated; VCC1 = VCC2 = 5 V; ICC1 = ICC2 = 100 A; CLK1 and CLK2 stopped VDD = 3.3 V; active mode; VCC1 = VCC2 = 5 V; ICC1 + ICC2 = 80 mA; CLK1 = CLK2 = 5 MHz VDD = 3.3 V; active mode; VCC1 = VCC2 = 3 V; ICC1 = ICC2 = 10 mA; CLK1 = CLK2 = 5 MHz VCC1, VCC2 supply voltage for card 1 and 2 note 1 5 V card 3 V card ICC1, ICC2 Vth1 Vhys1 Tamb Note supply current for card 1 and 2 threshold voltage for the supervisor on VDD hysteresis on Vth1 ambient temperature 4.75 2.80 0 2.1 50 -25 CONDITIONS MIN. 2.5 1.5 - - TDA8020HL TYP. - - - - MAX. UNIT 6.5 VDD 150 2 V V A mA - - 400 mA - - 80 mA - - - - - - 5.25 3.20 55 2.4 100 +85 V V mA V mV C 1. Both cards are not allowed to operate at maximum current at the same time at minimum supply voltage. 2001 Aug 15 3 Philips Semiconductors Product specification Dual smart card interface BLOCK DIAGRAM TDA8020HL handbook, full pagewidth VDD 20 SAP 14 SAM 19 SBP 15 SBM 17 16 CDEL 30 SUPPLY SUPERVISOR VOLTAGE REFERENCE DC/DC CONVERTER 13 VDDA VUP TDA8020HL 3 INTERNAL OSCILLATOR CLOCK CIRCUITRY 5 4 CARD1 DRIVERS SAD0 SAD1 SCL SDA IRQ 23 32 24 21 22 25 9 CLOCK CIRCUITRY CLKIN2 CLKIN1 I/O1uC I/O2uC VDDI 31 27 28 LEVEL SHIFTERS SEQUENCER2 29 10 26 CARD2 DRIVERS 8 6 I/O2 7 PRES2 11 CLK2 RST2 VCC2 CGND2 I 2C-BUS AND REGISTERS SEQUENCER1 1 2 CLK1 RST1 VCC1 CGND1 I/O1 PRES1 18 12 FCE834 AGND GND Fig.1 Block diagram. 2001 Aug 15 4 Philips Semiconductors Product specification Dual smart card interface PINNING SYMBOL PRES1 CGND1 CLK1 VCC1 RST1 I/O2 PRES2 CGND2 CLK2 VCC2 RST2 GND VUP SAP SBP VDDA SBM AGND SAM VDD SCL SDA SAD0 SAD1 IRQ CLKIN1 I/O1uC I/O2uC CLKIN2 CDEL VDDI I/O1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION card 1 presence contact input (active HIGH) ground connection output to card 1 (C5 contact) clock output to card 1 (C3 contact) TDA8020HL supply voltage output to card 1 (C1 contact); decouple to pin CGND1 with 2 x 100 nF capacitors with ESR < 100 m reset output to card 1 (C2 contact) I/O contact to card 2 (C7 contact); internal 15 k pull-up resistance to pin VCC2 card 2 presence contact input (active HIGH) ground connection output to card 2 (C5 contact) clock output to card 2 (C3 contact) supply voltage output to card 2 (C1 contact); decouple to pin CGND2 with 2 x 100 nF capacitors with ESR < 100 m reset output to card 2 (C2 contact) ground connection output of DC/DC converter; a 220 nF capacitor with ESR < 100 m must be connected to pin AGND capacitors connection for the DC/DC converter; a 220 nF capacitor with ESR < 100 m must be connected between pins SAP and SAM capacitors connection for the DC/DC converter; a 220 nF capacitor with ESR < 100 m must be connected between pins SBP and SBM analog supply voltage for the DC/DC converter capacitors connection for the DC/DC converter; a 220 nF capacitor with ESR < 100 m must be connected between pins SBP and SBM analog ground connection for the DC/DC converter capacitors connection for the DC/DC converter; a 220 nF capacitor with ESR < 100 m must be connected between pins SAP and SAM power supply voltage serial clock input of the I2C-bus (open drain) serial data input/output of the I2C-bus (open drain) I2C-bus address selection input 0 I2C-bus address selection input 1 interrupt request output to host (open drain; active LOW) external clock input for card 1 I/O connection to host for card 1; internal 22 k pull-up resistor to VDDI I/O connection to host for card 2; internal 22 k pull-up resistor to VDDI external clock input for card 2 delay capacitor connection for the voltage supervisor (1 ms per 2 nF) interface signals reference supply voltage I/O contact to card 1 (C7 contact); internal 15 k pull-up resistor to VCC1 2001 Aug 15 5 Philips Semiconductors Product specification Dual smart card interface TDA8020HL 29 CLKIN2 30 CDEL 32 I/O1 31 VDDI handbook, full pagewidth 26 CLKIN1 28 I/O2uC 27 I/O1uC PRES1 CGND1 CLK1 VCC1 RST1 I/O2 PRES2 CGND2 1 2 3 4 25 IRQ 24 SAD1 23 SAD0 22 SDA 21 SCL TDA8020HL 5 6 7 8 20 VDD 19 SAM 18 AGND 17 SBM VCC2 10 RST2 11 GND 12 VUP 13 SAP 14 SBP 15 VDDA 16 9 FCE833 CLK2 Fig.2 Pin configuration. 2001 Aug 15 6 Philips Semiconductors Product specification Dual smart card interface FUNCTIONAL DESCRIPTION Throughout this specification, it is assumed that the reader is familiar with ISO 7816 norm terminology. Supply The TDA8020HL operates with a supply voltage from 2.5 to 6.5 V. An integrated voltage supervisor ensures that no spike appears on cards contacts during power-on or off. The supervisor also initializes the device, and forces an automatic emergency deactivation of the contacts in the event of a supply drop-out. As long as the supply voltage is below the threshold voltage Vth1, the capacitor CDEL remains uncharged. When the supply voltage reaches Vth1 and Vhys1, then CDEL is charged with a small current source of approximately 2 A. When the voltage on CDEL reaches Vth2, then the supervisor is no longer active. As long as the supervisor is active (pin IRQ is LOW), bit SUPL in the status register is set. When pin IRQ goes HIGH the supervisor becomes inactive (see Fig.3). Separate supply pins are used for the DC/DC converter, allowing specific decoupling for counteracting the noise the switching transistors may induce on the supply. TDA8020HL A specific reference supply voltage, VDDI, is used for the interface signals CLKIN1, CLKIN2, I/O1uC, I/O2uC, SAD0, SAD1, SCL, SDA and IRQ, which can be lower than VDD (minimum 1.5 V), thus allowing direct control with a low voltage supplied device. Pins SCL, SDA and IRQ are open-drain outputs, and may be externally pulled up to a voltage higher than VDD. I2C-bus A 400 kHz I2C-bus slave interface is used for configuring the device and reading the status. The bus has 2 addresses, one for each card. 4 devices may be used in parallel due to the address selection pins SAD0 and SAD1 (see Table 1). Table 1 Proposed addresses PIN SAD0 LOW HIGH LOW HIGH CARD 1 40H 42H 44H 46H CARD 2 48H 4AH 4CH 4EH PIN SAD1 LOW LOW HIGH HIGH handbook, full pagewidth VDD Vth1 + Vhys1 Vth1 Vth2 VCDEL IRQ tw tw status read after event BUS NOT RESPONDING BUS OK BUS NOT RESPONDING BUS OK BUS NOT RESPONDING FCE835 Fig.3 Supply supervisor. 2001 Aug 15 7 Philips Semiconductors Product specification Dual smart card interface WRITING COMMANDS START, ADDRESS, WRITE, CONTROL byte, STOP. Table 2 CONTROL bits (all bits cleared after power-on) BIT 0 1 2 3 4 5 6 7 DESCRIPTION TDA8020HL NAME START/STOP WARM 3 and 5 V PDOWN CLKPD CLKSEL1 CLKSEL2 I/OEN when set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence when set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute when set, VCC = 3 V; when reset, VCC = 5 V when set, the configuration defined by bit CLKPD is applied on pin CLK, and the circuit enters the Power-down mode; when reset, the circuit goes back to normal (active) mode when set, CLK is stopped HIGH during Power-down mode; when reset, CLK is stopped LOW in Power-down mode bits 5 and 6 determine the clock to the card in normal mode according to Table 3 when set, I/O is transferred on I/OuC; when reset, I/O to I/OuC is high-impedance All frequency changes are synchronous, thus ensuring that no pulse is shorter than 45% of the smallest period. For cards power reduction modes, CLKIN may be stopped after switching to STOP LOW or STOP HIGH. CLKIN should be restarted before leaving this mode. A correct duty factor can not be guaranteed in the CLKIN configuration, as it depends on the duty factor of the CLKIN signal. When deactivating the card, by resetting the START bit, only bit 0 must be changed. The clock to the cards in active mode is selected with bits CLKSEL1 and CLKSEL2; see Table 3. Table 3 Selecting the card clock. BIT CLKSEL1 0 1 0 1 CLOCK OUTPUT CLKIN/8 CLKIN/4 CLKIN/2 CLKIN BIT CLKSEL2 0 0 1 1 2001 Aug 15 8 Philips Semiconductors Product specification Dual smart card interface READING STATUS START, ADDRESS, READ, STATUS byte, STOP. Table 4 STATUS bits (all bits cleared after power-on, except SUPL and PRES) BIT 0 1 2 3 4 5 6 7 DESCRIPTION set when the card is present; reset when the card is not present TDA8020HL NAME PRES PRESL I/O SUPL PROT MUTE EARLY ACTIVE set when the card has been inserted or extracted; reset when the status has been read set when I/O is HIGH and reset if I/O is LOW set when the supervisor has signalled a fault; reset when the status has been read set when an overload or an overheating has occurred during a session; reset when the status has been read set during ATR when the selected card has not answered during the ISO 7816 time slots set during ATR when the selected card has answered too early set if the card is active; reset if the card is inactive When one of the bits PRESL, MUTE, EARLY and PROT is set, then pin IRQ goes LOW until the status byte has been read. After power-on, bit SUPL is set until the status byte has been read, and pin IRQ is LOW until the supervisor becomes inactive. DC/DC converter VCC1 is the supply voltage for card 1 contacts, VCC2 for card 2 contacts. Card 1 and card 2 may be independently powered-down, powered at 5 V or powered at 3 V. A capacitor type step-up converter is used for generating these voltages. This step-up converter acts either as a doubler, tripler or follower. If VCC is the maximum value of VCC1 and VCC2, then there are 4 possible situations: * VDD = 3 V and VCC = 3 V: in this case, the DC/DC converter acts as a doubler with a regulation of approximately 4.0 V * VDD = 3 V and VCC = 5 V: in this case, the DC/DC converter acts as a tripler with a regulation of approximately 5.5 V * VDD = 5 V and VCC = 3 V: in this case, the DC/DC converter acts as a follower: VDD is applied on VUP * VDD = 5 V and VCC = 5 V: in this case, the DC/DC converter acts as a doubler with a regulation of approximately 5.5 V. The switch between the modes is automatically executed when VDD is approximately 3.4 V. Each card may independently draw a current up to 65 mA, also during activation, with a supply voltage from 2.5 V up to 6.5 V provided the sum of ICC1 and ICC2 does not exceed 80 mA. If VDD > 3 V, for 5 V cards, then both cards can draw up to 55 mA at the same time. If VDD > 3.3 V, for 3 V cards, then both cards can draw up to 50 mA at the same time. The DC/DC converter is powered with specific pins (VDDA and AGND) to enable separate decoupling. The output voltage, VUP, is internally fed to the VCC generators. VCC1, VCC2 and CGND1, CGND2 are used as a reference for all other cards contacts. Sequencers and clock counter Two sequencers are used to ensure activation and deactivation sequences according to ISO 7816 and EMV norms, even in the event of an emergency (card removal during transaction, supply drop-out and hardware problem). The sequencers are clocked by the internal oscillator. The activation of a card is initiated by setting the card select bit and the start bit within the control register. This is only possible if the card is present and if the voltage supervisor is not active. During activation the DC/DC converter is initiated (except if another card is already powered up or if VDD = 5 V and VCC = 3 V). VCC then goes high to the selected voltage (3 or 5 V), the I/O lines are then enabled and the clock is started with RST LOW. 9 2001 Aug 15 Philips Semiconductors Product specification Dual smart card interface If a start bit is detected on the I/O during the first 200 CLK pulses, then it is omitted. If a start bit is detected between 200 and 352 CLK pulses, then bit EARLY is set in the status register. If the card starts answering before 41950 CLK pulses, then RST remains LOW level. If not, after 41950 CLK pulses, RST is toggled HIGH. If, again, a start bit is detected within 352 CLK pulses, bit EARLY is set in the status register. If the card does not answer before 41950 new CLK pulses, then bit MUTE is set in the status register. If the card answers within the correct window, then the CLK count is stopped and the system controller may send commands to the card. Deactivation is initiated either by the system controller (reset bit START), or automatically in the event of a hardware problem or supply drop-out. With a supply drop-out both cards are deactivated at the same time. During deactivation, RST goes LOW, the clock is stopped and the I/O lines go LOW. VCC then goes low with a controlled slope and the DC/DC converter is stopped if no card is active. Outside a session, cards contacts are forced low impedance to CGND. Activation sequence TDA8020HL When the cards are inactive, VCC, CLK, RST and I/O are LOW, with low impedance with respect to CGND. The DC/DC converter is stopped. When everything is satisfactory (voltage supply, card present and no hardware problems), the system controller may initiate an activation sequence of a present card (see Fig.4): * The DC/DC converter is started (t1). If one card was already active, then the DC/DC converter was already on, and nothing more occurs at this step * VCC starts rising from 0 to 5 or 3 V with a controlled rise time of 0.14 V/s typical (t2) * I/O rises to VCC (t3); internal 10 k pull-up resistors to VCC * CLK is sent to the card and RST is enabled (t4 = tact). If the card does not answer within the first 41950 CLK cycles, then RST is raised HIGH (t5). The sequencer is clocked by fint/64 which leads to a time interval T of 25 s typical. Thus t1 = 0 to T/64; t2 = t1 + 3T/2; t3 = t1 + 7T/2 and t4 = t1 + 4T. handbook, full pagewidth START/STOP VUP VCC I/O CLK RST t0 t1 t2 t3 t4 t5 ATR FCE837 t4 = tact. Fig.4 Activation sequence. 2001 Aug 15 10 Philips Semiconductors Product specification Dual smart card interface Deactivation sequence When the session is completed, the microcontroller resets bit START/STOP to logic 0 (t10). The circuit then executes an automatic deactivation sequence (see Fig.5): * Card reset (RST falls LOW) (t11) * CLK is stopped (t12) * I/O falls to 0 V (t13) * VCC falls to 0 V with typical 0.14 V/s slew rate (t14) * The DC/DC converter is stopped (if both cards are inactive) and CLK, RST, VCC and I/O become low impedance to CGND (t15). TDA8020HL t11 = t10 + T/64; t12 = t11 + T/2; t13 = t11 + T; t14 = t11 + 3T/2; t15 = t11 + 7T/2. The deactivation time tde is the time that VCC needs to drop below 0.4 V from START/STOP to logic 0 (t10). handbook, full pagewidth START/STOP RST CLK I/O VCC VUP t de t10 t11 t12 t13 t14 t15 FCE836 Fig.5 Deactivation sequence. 2001 Aug 15 11 Philips Semiconductors Product specification Dual smart card interface Protections The current on pin CLK is limited to 70 mA. The current on pin RST is limited to 20 mA; if the current reaches this value with RST LOW, then an emergency deactivation sequence is performed, IRQ is pulled LOW and bit PROT is set in the status register. The current on pins I/O is limited to +15 and -15 mA. The current on VCC is limited to 90 mA; if ICC reaches this value, then an emergency deactivation sequence is performed, IRQ is pulled LOW and bit PROT is set in the status register. In the event of overcurrent on VCC, card take-off during a session, overheating, or overcurrent on RST, then the TDA8020HL performs an automatic emergency deactivation sequence on the corresponding card, resets bit START/STOP and pulls pin IRQ LOW. In the event of overheating or supply drop-out, the TDA8020HL performs an automatic emergency deactivation sequence on both cards, resets both bits START/STOP and pulls pin IRQ LOW. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD VDDI Vn PARAMETER supply voltage on pins VDD and VDDA supply voltage for interface signals input voltage on pins SAP, SAM, SBP, SBM and VUP on all other pins In DC current from or to pins SAP, SAM, SBP, SBM and VUP from or to all other pins Ptot Tstg Tj Ves total power dissipation storage temperature junction temperature electrostatic discharge voltage on pins I/O1, VCC1, RST1, CLK1, CGND1, PRES1, I/O2, VCC2, RST2, CLK2, CGND2 and PRES2 on all other pins -6 Tamb = -20 to +85 C -200 -5 - -55 - -0.5 -0.5 CONDITIONS MIN. -0.5 -0.5 TDA8020HL Clock inputs and data inputs/outputs to the system controller CLKIN1 is the input clock for card 1, CLKIN2 for card 2. They may be driven separately from the system controller, or be tied together externally and driven with the same signal. An RC filter is needed on these lines in order to limit the influence of possible fast transitions. I/O1uC is the data signal to or from card 1, I/O2uC to or from card 2. They can be driven separately from the system controller, in which case both bits I/OEN may be set to logic 1. They can also be driven by the same signal, in which event they have to be tied together externally, but each bit I/OEN has to be set or reset according to the addressed card. MAX. +6.5 +6.5 +7.5 V V V UNIT VDD + 0.5 V +200 +5 460 +150 125 +6 mA mA mW C C kV -2 +2 kV 2001 Aug 15 12 Philips Semiconductors Product specification Dual smart card interface THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 80 TDA8020HL UNIT K/W CHARACTERISTICS VDD = 3.3 V; VDDI = 1.5 V; fCLKIN1 = fCLKIN2 = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Temperature Tamb Supply VDD IDD supply voltage on pins VDD and VDDA supply current (IDD and IDDA) inactive mode Power-down mode; 2 cards activated; VCC1 = VCC2 = 5 V; ICC1 = ICC2 = 100 A; CLK1 and CLK2 stopped active mode; VCC1 = VCC2 = 5 V; ICC1 + ICC2 = 80 mA; CLK1 = CLK2 = 5 MHz active mode; VCC1 = VCC2 = 3 V; ICC1 = ICC2 = 10 mA; CLK1 = CLK2 = 5 MHz VDDI IDDI Vth1 Vhys1 Vth2 VCDEL ICDEL tW supply voltage for interface signals supply current for interface signals threshold voltage on VDD hysteresis on Vth1 threshold voltage on pin CDEL voltage on pin CDEL output current at pin CDEL width of the internal ALARM pulse pin grounded (charge) VCDEL = VDD (discharge) CDEL = 22 nF falling 2.5 - - - - - 6.5 150 2.5 V A mA ambient temperature -25 - +85 C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - - 400 mA - - 80 mA 1.5 - 2.1 50 - - - - - - - - - 1.38 - -2 5 10 VDD 120 2.4 100 - VDD + 0.3 - - - V A V mV V V A mA ms DC/DC converter fint VUP Vdt internal oscillator frequency voltage on pin VUP detection voltage for doubler, tripler and follower selection at least one 5 V card both cards 3 V 2 - - - 2.5 5.5 4 3.4 3 - - - MHz V V V 2001 Aug 15 13 Philips Semiconductors Product specification Dual smart card interface TDA8020HL SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - 5 MAX. UNIT Card supply voltages (pins VCC1 and VCC2); note 1 Vo(inactive) Iinactive VCC(ripple) output voltage in inactive mode current from VCC when inactive output voltage including ripple no load Iinactive = 1 mA pin grounded active mode; ICC < 65 mA; 5 V card; ICC1 + ICC2 < 80 mA; 2.5 V < VDD < 6.5 V active mode; ICC < 65 mA; 3 V card; ICC1 + ICC2 < 80 mA; 2.5 V < VDD < 6.5 V active mode; current pulses of 40 nAs with I < 200 mA and t < 400 ns; f < 20 MHz; 5 V card active mode; current pulses of 24 nAs with I < 200 mA and t < 400 ns; f < 20 MHz; 3 V card VCC(load) output voltage when both slots fully loaded active mode; VDD > 3 V; ICC1 < 55 mA; ICC2 < 55 mA; 5 V cards active mode; VDD > 3.3 V; ICC < 50 mA; ICC2 < 50 mA; 3 V cards ICC output current 0 0 - 4.75 0.1 0.3 -1 5.25 V V mA V 2.8 3 3.2 V 4.6 - 5.4 V 2.76 - 3.24 V 4.6 - 5.4 V 2.76 - 3.24 V from 0 to 5 V (5 V card); the other - card at full load; VDD > 3 V from 0 to 3 V (3 V card); the other - card at full load; VDD > 3.3 V VCC shorted to GND - - 0.08 - - - - 0.14 -55 -50 -100 350 0.20 mA mA mA mV V/s Vripple(p-p) SR ripple voltage (peak-to-peak value) slew rate from 20 kHz to 200 MHz up or down (maximum capacitance is 300 nF) Reset output to the cards (pins RST1 and RST2) Vo(inactive) Iinactive VOL VOH tr tf output voltage in inactive mode current from pin RST when inactive LOW-level output voltage HIGH-level output voltage rise time fall time no load Iinactive = 1 mA pin grounded IOL = 200 A IOH < -200 A CL = 30 pF CL = 30 pF 0 0 0 0 VCC - 0.5 - - - - - - - - - 0.1 0.3 -1 0.3 VCC 0.1 0.1 V V mA V V s s 2001 Aug 15 14 Philips Semiconductors Product specification Dual smart card interface TDA8020HL SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - - - - - - - - - - 500 MAX. UNIT Clock output to the cards (pins CLK1 and CLK2) Vo(inactive) Iinactive VOL VOH tr tf fclk SR output voltage in inactive mode current from pin CLK when inactive LOW-level output voltage HIGH-level output voltage rise time fall time clock frequency duty factor slew rate (rise and fall) no load Iinactive = 1 mA pin grounded IOL = 200 A IOH < -200 A CL = 30 pF CL = 30 pF 1 MHz Idle configuration operational CL = 30 pF CL = 30 pF no load Iinactive = 1 mA pin grounded IOL = 1 mA no DC load IOH < -20 A IOH < -40 A Iedge td(edge) current from pins I/O1 VOH = 0.9VCC; CL = 80 pF and I/O2 when active pull-up delay between falling edge on pins I/O1, I/O2, I/O1uC, I/O2uC and width of active pull-up pulse LOW-level input voltage HIGH-level input voltage LOW-level input current on pin I/O HIGH-level input leakage current on pin I/O input transition times output transition times VIL = 0 VIH = VCC from VIL(max) to VIH(min) CL < 80 pF; no DC load; 10% to 90% from 0 to VCC1 and VCC2 0 0 0 0 VCC - 0.5 - - 1 0 45 0.2 0.1 0.3 -1 0.3 VCC 8 8 1.5 10 55 - 0.1 0.3 -1 0.3 VCC + 0.1 VCC + 0.1 VCC + 0.1 - 650 V V mA V V ns ns MHz MHz % V/ns Data lines (pins I/O1 and I/O2); note 2 Vo(inactive) Iinactive VOL VOH output voltage in inactive mode current from pin I/O when inactive LOW-level output voltage HIGH-level output voltage 0 - - 0 0.9VCC 0.8VCC 0.75VCC -1 - V V mA V V V V mA ns VIL VIH IIL ILIH ti(r), ti(f) to(r), to(f) -0.3 1.5 - - - - - - - - - - +0.8 VCC 600 10 1.5 0.1 V V A A s s Ci Rpu(int) input capacitance on pins I/O1 and I/O2 internal pull-up resistance between pin I/O and VCC - 12 - 15 10 18 pF k 2001 Aug 15 15 Philips Semiconductors Product specification Dual smart card interface TDA8020HL SYMBOL fmax PARAMETER maximum frequency on pins I/O1 and I/O2 CONDITIONS - MIN. TYP. - MAX. 500 UNIT kHz Data lines (pins I/O1uC and I/O2uC); note 3 VOL VOH VIL VIH IIL ILIH ti(r), ti(f) to(r), to(f) Rpu(int) Timing tact tde activation sequence duration deactivation sequence duration - - - - 135 110 s s LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current input transition times output transition times internal pull-up resistance VIL = 0 VIH = VDDI from VIL(max) to VIH(min) CL < 30 pF; 10% to 90% from 0 to VDDI IOL = 1 mA no DC load IOH < -10 A 0 0.9VDDI 0.75VDDI -0.3 0.7VDDI - - - - - - - - - - - - - 22 0.4 VDDI + 0.2 VDDI + 0.2 0.25VDDI VDDI + 0.3 600 10 1 0.1 30 V V V V V A A s s k between I/O1uC, I/O2uC and VDDI 15 Protections and limitations ICC(sd) II/O(lim) ICLK(lim) IRST(sd) shutdown and limitation current at VCC1 and VCC2 limitation current on pins I/O1 and I/O2 limitation current on pins CLK1 and CLK2 shutdown and limitation current on pins RST1 and RST2 shutdown die temperature - -15 -70 -20 -90 - - - - +15 +70 +20 mA mA mA mA Tj(sd) VIL VIH ILIL ILIH - - 0.7VDD VI = 0 VI = VDD - - 150 - - - - - 0.3VDD - 20 20 C V V A A Card presence inputs (pins PRES1 and PRES2) LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current 2001 Aug 15 16 Philips Semiconductors Product specification Dual smart card interface TDA8020HL SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - - - - - - - - - - - MAX. UNIT Clock inputs (pins CLKIN1 and CLKIN2) fext VIL VIH ti(r), ti(f) VIL VIH ILIL ILIH Ci VOL ILH VIL VIH ILH IIL VOL VIL VIH ILH IIL Notes 1. Two ceramic multilayer capacitors of minimum 100 nF with low ESR should be used in order to meet these specifications. 2. Pin I/O1 has an internal 15 k pull-up resistor to VCC1 and pin I/O2 has an internal 15 k pull-up resistor to VCC2. 3. Pins I/O1uC and I/O2uC have an internal 22 k pull-up resistor to VDDI. external frequency applied on CLKIN1 and CLKIN2 LOW-level input voltage HIGH-level input voltage input transition times 0 0 0.7VDDI - -0.3 0.7VDDI - - - Io = 2 mA - - -0.3 0.7VDDI - depends on the pull-up resistance - IOL = 3 mA - -0.3 0.7VDDI - depends on the pull-up resistance - 25 0.25VDDI VDDI + 0.3 100 MHz V V ns Logic inputs (pins SAD0 and SAD1) LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current input capacitance 0.25VDDI VDDI + 0.3 20 20 10 V V A A pF Interrupt line (pin IRQ; open-drain; active LOW output) LOW-level output voltage HIGH-level leakage current 0.3 10 V A V V A V Serial data input/output (pin SDA; open-drain) LOW-level input voltage HIGH-level input voltage HIGH-level leakage current LOW-level input current LOW-level output voltage 0.25VDDI VDDI + 0.3 1 - 0.3 Serial clock input (pin SCL; open-drain) LOW-level input voltage HIGH-level input voltage HIGH-level leakage current LOW-level input current 0.25VDDI VDDI + 0.3 1 - V V A 2001 Aug 15 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth CLKIN2 CLKIN1 I/O2uC I/O1uC CDEL VDDI I/O1 IRQ MICROCONTROLLER RST2 SAP CLK2 VCC2 GND VUP SBP VDDA 2001 Aug 15 0 k +3.3 V +1.5 V 10 F (16 V) C4 C3 C2 C1 C5I C6I C7I C8I C8 C7 C6 C5 C1I C2I C3I C4I APPLICATION INFORMATION Philips Semiconductors Dual smart card interface +1.5 to +6.5 V +1.5 V CARD_READ_LM01 100 nF 100 k 100 nF 22 nF P1_0 1 P1_1 2 P1_2 3 P1_3 4 P1_4 5 P1_5 6 P1_6 7 P1_7 8 RST 9 P3_0 10 P3_1 11 P3_2 12 P3_3 13 P3_4 14 P3_5 15 P3_6 16 P3_7 17 XTAL2 18 XTAL1 19 VSS 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 EA ALE PSEN P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 220 1 k 10 pF 24 23 22 21 SAD1 SAD0 SDA SCL VDD SAM AGND SBM 220 nF +1.5 V 1.5 to 6.5 k PRES1 K1 K2 32 1 2 3 4 31 30 29 28 27 26 25 CGND1 CLK1 10 F CARD 1 VCC1 100 nF RST1 I/O2 0 k 100 k CARD_READ_LM01 C4 C3 C2 C1 C5I C6I C7I C8I C8 C7 C6 C5 C1I C2I C3I C4I TDA8020HL 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 18 100 nF K1 K2 PRES2 CGND2 220 nF 33 pF 100 nF 220 nF 14.745 MHz 100 nF 100 nF 10 F (16 V) 33 pF FCE838 CARD 2 100 k +3.3 V +3.3 V 33 F (16 V) +3.3 V TDA8020HL Product specification Fig.6 Application diagram. Philips Semiconductors Product specification Dual smart card interface PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm TDA8020HL SOT358-1 c y X 24 25 17 16 ZE A e E HE wM bp pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X L Lp A A2 A 1 (A 3) 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC 136E03 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 2001 Aug 15 19 Philips Semiconductors Product specification Dual smart card interface SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. TDA8020HL If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Aug 15 20 Philips Semiconductors Product specification Dual smart card interface Suitability of surface mount IC packages for wave and reflow soldering methods TDA8020HL SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2001 Aug 15 21 Philips Semiconductors Product specification Dual smart card interface DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS TDA8020HL Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Aug 15 22 Philips Semiconductors Product specification Dual smart card interface NOTES TDA8020HL 2001 Aug 15 23 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp24 Date of release: 2001 Aug 15 Document order number: 9397 750 08605 |
Price & Availability of TDA8020
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |